Reduced latency I/O in multi-actuator device
US10720200B2 · kind B2 · utility
5Cited by
17References
22Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 25, 2018 |
| Grant date | Jul 21, 2020 |
| Priority date | — |
| Expiry date | Apr 25, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An exemplary data refresh method disclosed herein reading data into volatile memory from a first storage region using a read element controlled by a first actuator assembly and writing the data from the volatile memory to a second storage region using a write element controlled by a second actuator assembly, where the first actuator assembly and the second actuator assembly are configured to receive data from control circuitry via independent read/write communication channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.