Impedance matching network and method
US10720309B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2020 |
| Grant date | Jul 21, 2020 |
| Priority date | — |
| Expiry date | Apr 8, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/334
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present disclosure is directed to a method for impedance matching. The RF source provides at least two repeating, non-zero pulse levels, including a high-priority pulse level and a low-priority pulse level. The matching network comprises at least one EVC, which comprises discrete capacitors configured to switch in and out to provide a plurality of match configurations. Each EVC has a switching limit comprising a predetermined number of switches in or out of the EVC's discrete capacitors in a prior time interval. Upon determining that switching to a new match configuration would cause an EVC to reach the switching limit, the method determines whether the new match configuration is for the low- or high-priority pulse level. If for the low-priority pulse level, the method prevents the switching of the EVC. If for the high-priority pulse level, the method switches the EVC to the new match configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.