Three-dimensional semiconductor memory device
US10720441B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2018 |
| Grant date | Jul 21, 2020 |
| Priority date | — |
| Expiry date | May 24, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a three-dimensional semiconductor memory device. The device may include a substrate that includes a cell array region and a connection region; an electrode structure provided on the substrate to extend in a first direction and include electrodes that are vertically stacked on the substrate and include pad portions which are stacked on the connection region to have a staircase structure; cell vertical structures provided on the cell array region to penetrate the electrode structure; dummy vertical structures provided on the connection region to penetrate the pad portion of each electrode; and cell contact plugs coupled to the pad portions of the electrodes. Each cell contact plug may have a non-circular top surface, and the dummy vertical structures may be arranged to surround each cell contact plug, in a plan view.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.