Integrated trench capacitor formed in an epitaxial layer
US10720490B2 · kind B2 · utility
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3References
20Claims
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Assignee
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Key dates
| Filing date | Jan 2, 2020 |
| Grant date | Jul 21, 2020 |
| Priority date | — |
| Expiry date | Jan 2, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A trench capacitor includes at least one epitaxial semiconductor surface layer on a semiconductor substrate having a doping level that is less than a doping level of the semiconductor substrate. A plurality of trenches are formed through at least one half of a thickness of the epitaxial semiconductor surface layer. The epitaxial semiconductor surface layer is thicker than a depth of the plurality of trenches. At least one capacitor dielectric layer lines a surface of the trenches. At least one trench fill layer on the dielectric layer fills the trenches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.