Semiconductor device having polysilicon field plate for power MOSFETs

US10720499B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Ya-Ping Chen · Chengdu, CN
• Hong-Seon Yang · Yongsan-gu, KR
• Peng Li · 流花街道, CN
• Seetharaman Sridhar · Richardson, US
• Yunlong Liu · Chengdu, CN
• Rui Liu · Nanhu, CN

Key dates

• Filing date: Jul 23, 2018
• Grant date: Jul 21, 2020
• Expiry date: Jul 23, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/31116
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor device includes a substrate including a semiconductor surface layer. A field plate (FP) includes a trench in the semiconductor surface layer filled with a single polysilicon layer positioned on at least one side of a power metal-oxide-semiconductor field effect transistor (power MOSFET). The power MOSFET includes a dielectric liner lining a sidewall of the trench under the polysilicon layer including a second dielectric liner on a first dielectric liner. An upper portion of the dielectric liner has a lower dielectric thickness as compared to a dielectric thickness on its lower portion. The single polysilicon layer extends continuously over the dielectric liner along both the lower portion and the upper portion. The power MOSFET includes a drain including a drain contact below a vertical drift region in the semiconductor surface layer, and a gate, body and a source above the vertical drift region.