Method of controlling wafer bow in a type III-V semiconductor device
US10720520B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2017 |
| Grant date | Jul 21, 2020 |
| Priority date | — |
| Expiry date | Aug 24, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A type IV semiconductor substrate having a main surface is provided. A type III-V semiconductor channel region that includes a two-dimensional carrier gas is formed over the type IV semiconductor substrate. A type III-V semiconductor lattice transition region that is configured to alleviate mechanical stress arising from lattice mismatch is formed between the type IV semiconductor substrate and the type III-V semiconductor channel region. Forming the type III-V semiconductor lattice transition region includes forming a first lattice transition layer having a first metallic concentration over the type IV semiconductor substrate, forming a third lattice transition layer having a third metallic concentration that is higher than the first metallic concentration over the first lattice transition layer, and forming a fourth lattice transition layer having a fourth metallic concentration that is lower than the first metallic concentration over the third lattice transition layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.