Split-gate enhanced power MOS device

US10720524B1 · kind B1 · utility

Assignee

• University of Electronic Science and Technology of China · CN

Inventors

• Ming Qiao · Chengdu, CN
• Zhengkang Wang · Chengdu, CN
• Dong Fang · Wuxi, CN
• Ruidi WANG · Tianjin, CN
• Bo Zhang · Shanghai, CN

Key dates

• Filing date: Aug 9, 2019
• Grant date: Jul 21, 2020
• Expiry date: Aug 9, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/256

Abstract

A split-gate enhanced power MOS device includes a substrate and an epitaxial layer formed on an upper surface of the substrate. A control gate trench is provided in the epitaxial layer. The control gate trench includes a gate electrode and a split-gate electrode. The gate electrode includes a first gate electrode and a second gate electrode. The first gate electrode and the second gate electrode are located in an upper half portion of the control gate trench and are separated by a first dielectric layer. The first gate electrode and the second gate electrode are located above the split-gate electrode and are separated from the split-gate electrode by a second dielectric layer. The first gate electrode and the second gate electrode are separated from a body region in the epitaxial layer by a gate dielectric.