Comparator error suppression
US10720933B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 2, 2017 |
| Grant date | Jul 21, 2020 |
| Priority date | — |
| Expiry date | Nov 2, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/468
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Comparator input noise or offset suppression can include an error detector circuit that can operate in a feedback loop, such as during an autozero phase. The error detector circuit can include a time-varying filter response to improve accuracy and convergence time. The comparator can be used in a successive approximation routine (SAR) or other analog-to-digital converter (ADC) circuit, such as to control a digital-to-analog converter (DAC), such as can be used to adjust a tuning circuit within the comparator to compensate for noise or offset. The DAC can be combined with a DAC used for carrying out SAR bit-trials or bit decisions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.