Patent · US Active

Addressable test chip with sensing circuit

US10725102B2 · kind B2 · utility

0Cited by
1References
20Claims
0Family size

Assignee

Inventor

Key dates

Filing dateApr 8, 2019
Grant dateJul 28, 2020
Priority date—
Expiry dateApr 8, 2039

Classification

  • Technology area (CPC Y)Emerging Cross-Sectional Technologies
  • CPC primaryY02D10/00
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

An address register includes a plurality of edge-triggered flip-flop registers having an input D, an input R, an input CK, and an output Q; a counter logic; a shifter logic; a multiplexer; input ports including a reset signal RST, a clock signal CLK, a shift enable signal SE, a shift data input signal SI; an output port including address signals ADDR. D is coupled to a data output of the multiplexer; R is coupled to a reset (RST) pad; CK is coupled to a clock (CLK) pad; Q is coupled to an address (ADDR) pad; an input of the counter logic is coupled to ADDR; an input of the shifter logic is coupled to ADDR and the shift data input signal SI; an input of the multiplexer is coupled to SE, an output of the counter logic, and an output of the shifter logic.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.