Signal processing system, signal processing circuit, and reset control method
US10725512B2 · kind B2 · utility
1Cited by
2References
15Claims
0Family size
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Key dates
| Filing date | Dec 29, 2017 |
| Grant date | Jul 28, 2020 |
| Priority date | — |
| Expiry date | Apr 8, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CPU needs to perform reset operation when a secondary arithmetic processing unit controlled by the CPU controls a signal processing circuit. CPU A controls module A. CPU B controls module B. Module A and module B control a signal processing circuit. CPU A and CPU B issue a reset request to the signal processing circuit. The signal processing circuit performs a reset process based on the reset request accepted from the CPU and a control origin identification signal that identifies a CPU as an origin of controlling the module having started a signal processing section.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.