Determining a power capping signal using direct memory access
US10725520B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2017 |
| Grant date | Jul 28, 2020 |
| Priority date | — |
| Expiry date | Oct 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/504
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Examples disclosed herein relate to determination of a power capping signal based on direct memory access. In an example, a hardware timer in a processor may generate a hardware trigger. In response to the hardware trigger, an analog-to-digital convertor (ADC) engine may obtain an analog voltage signal from a server. ADC engine may convert the analog voltage signal to a digital output. ADC engine may then generate a second hardware trigger. In response to the second hardware trigger, a direct memory access engine may provide the digital output to a programmable logic device via a direct memory access (DMA) operation. The programmable logic device may determine a power capping signal based on the digital output, and provide the power capping signal to the server.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.