Digital circuit with compressed carry
US10725741B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2018 |
| Grant date | Jul 28, 2020 |
| Priority date | — |
| Expiry date | Sep 21, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5443
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure pertain to digital circuits with compressed carries. In one embodiment, an adder circuit generates a sum and carry. The carry is compressed to reduce the number of bits required to represent the carry. In one embodiment, a multiplier circuit generates output product values. The output product values may be summed to produce a sum and carry. The carry may be compressed. In other embodiments, a multiplier circuit receives an input sum and compressed carry. The compressed input carry is decompressed and added to output product values and the input sum, and a resulting carry is compressed. The output of such a multiplier is another sum and compressed carry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.