Completion mechanism for a microprocessor instruction completion table
US10725786B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2018 |
| Grant date | Jul 28, 2020 |
| Priority date | — |
| Expiry date | Jan 24, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3854
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for a completion mechanism for a microprocessor are provided by marking entries in a section of an Instruction Completion Table (ICT) as ready to complete using corresponding Ready to Complete (RTC) status bits; determining a tail pointer indicating a start of the entries in the ICT that are ready for completion in a current clock cycle; performing a counting leading ones on an RTC vector that organizes the RTC status bits according to a program order for completing the entries to determine a count leading ones pointer that indicates an end of the entries in the ICT that are ready for completion in the current clock cycle; completing instructions included in the entries between the tail pointer and the count leading ones pointer in one clock cycle; and updating the tail pointer to a value of the count leading ones pointer for a subsequent clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.