Logical and physical address field size reduction by alignment-constrained writing technique
US10725931B2 · kind B2 · utility
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25Claims
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Key dates
| Filing date | Aug 22, 2018 |
| Grant date | Jul 28, 2020 |
| Priority date | — |
| Expiry date | Sep 29, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and arrangement are disclosed involving receiving a read-type command at a data storage arrangement, calculating a command span of the received read-type command and performing a look-up command, through use of a processor, for data located in each extent at a condensed logical block address state table for the read-type command, wherein the condensed logical block address state table describes a logical to physical table and at least one of transmitting data and displaying data related to the read-type command found in the condensed logical block address state table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.