Wafer-scale catalytic deposition of black phosphorus
US10727050B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2017 |
| Grant date | Jul 28, 2020 |
| Priority date | — |
| Expiry date | May 20, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/80
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for wafer-level deposition of a semiconductor layer structure including at least one two-dimensional black phosphorus layer. The method includes providing a wafer substrate and a metal catalyst layer on the substrate. The method includes heating a phosphorus material to generate a P4 flux and heating the P4 flux to generate a P2 flux, where the P2 flux is deposited on the metal catalyst layer using molecular beam epitaxy or chemical vapor deposition. The process of depositing the black phosphorus layer can include adding a dopant or alloy to the P2 flux to modify the band gap of the phosphorus layer. The method includes heating the substrate to a temperature above a temperature that causes red phosphorus to evaporate from the substrate, but does not cause black phosphorus to evaporate from the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.