Method for integrated circuit patterning

US10727061B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Tsung-Lin Yang · Tainan, TW
• Hua Feng Chen · Hsinchu, TW
• Kuei-Shun Chen · Baoshan, TW
• Min-Yann Hsieh · Baoshan, TW
• Po-Hsueh Li · Taichung, TW
• Shih-Chi Fu · Hengshan, TW
• Yuan-Hsiang Lung · Hsinchu, TW
• Yan-Tso Tsai · Baoshan, TW

Key dates

• Filing date: Apr 6, 2018
• Grant date: Jul 28, 2020
• Expiry date: Jun 29, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/32155
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An exemplary method includes forming a hard mask layer over an integrated circuit layer and implanting ions into a first portion of the hard mask layer without implanting ions into a second portion of the hard mask layer. An etching characteristic of the first portion is different than an etching characteristic of the second portion. After the implanting, the method includes annealing the hard mask layer. After the annealing, the method includes selectively etching the second portion of the hard mask layer, thereby forming an etching mask from the first portion of the hard mask layer. The method can further include using the etching mask to pattern the integrated circuit layer.