Three-dimensional semiconductor device and method of fabricating the same
US10727115B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2019 |
| Grant date | Jul 28, 2020 |
| Priority date | — |
| Expiry date | Jul 2, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a semiconductor device including a lower layer structure on a substrate, the lower layer structure having different thicknesses on first and second regions of the substrate, the lower layer structure including an electrode layer at a top and an insulating layer thereunder, an etch stop layer on the lower layer structure, an upper layer structure on the etch stop layer, the etch stop layer having an etch selectivity to the upper and lower layer structures, first and second contact plugs filling first and second openings defined in the upper layer structure and the etch stop layer on the first and second regions, respectively, and contacting corresponding electrode layers of the lower layer structure, respectively, such that one of the first and second contact plugs downwardly extends further with respect to a bottom of the etch stop layer than the other one of the first and second contact plugs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.