Die-in-die-cavity packaging
US10727203B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2018 |
| Grant date | Jul 28, 2020 |
| Priority date | — |
| Expiry date | May 8, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/10157
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system-in-package (SIP) incorporating die-in-die cavity packaging may include hybrid dies fabricated by milling or otherwise creating a cavity through the additive surfaces of a primary application specific integrated circuit (ASIC) die configured for flip-chip bonding and encapsulating a secondary die such as a Flash/non-volatile memory module, analog-digital converter (ADC), or other processing circuit into the cavity. The primary and secondary dies are then connected by the addition of redistribution layers. The resulting hybrid die may then be vertically integrated into the SIP along with additional memory modules or dies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.