Patent · US Active

Phase lock loop reference loss detection

US10727841B2 · kind B2 · utility

3Cited by

0References

20Claims

0Family size

Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Shailesh Ganapat Ghotgalkar · Bengaluru, IN
Wei Fu · San Diego, US
Venkatseema Das · Bengaluru, IN

Key dates

Filing date	Oct 22, 2018
Grant date	Jul 28, 2020
Priority date	—
Expiry date	Oct 22, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/18
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.