Phase-locked loop having a multi-band oscillator and method for calibrating same
US10727848B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2015 |
| Grant date | Jul 28, 2020 |
| Priority date | — |
| Expiry date | Jul 8, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop (PLL) comprising a multi-band oscillator and a memory configured to store control input for the oscillator. The PLL is operable in a calibration mode in which the PLL is configured to acquire a frequency controlled word (FCW) for the PLL corresponding to a frequency generated by the oscillator in response to a first control input threshold on a first band of the oscillator; generate a frequency corresponding to said FCW on a second band of the oscillator adjacent to said first band; identify a second control input causing the oscillator to generate said frequency corresponding to said FCW and store said second control input in memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.