Apparatus and methods for realization of N time interleaved digital-to-analog converters
US10727854B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2019 |
| Grant date | Jul 28, 2020 |
| Priority date | — |
| Expiry date | Jul 12, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/66
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Described herein are apparatus and methods for realization of time interleaved digital-to-analog converters (DACs) by detecting and aligning phase mismatches. In an implementation, a N-time interleaved DAC includes N DACs and N replica DACs, where a first set of N/2 DACs operate at a clock A and a second set of N/2 DACs operate at a clock B, and where N is at least two. The phase detector generates a phase detection output by comparing outputs of the first and second set of N/2 replica DACs with a multiplexor (MUX) clock, where the MUX clock is a multiple of a frequency of the clock A or the clock B. The clock A and the clock B are aligned with the MUX clock by advancing a phase of the clock A and the clock B until the phase detection output achieves a zero crossing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.