Loop delay compensation in a delta-sigma modulator
US10727859B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 26, 2019 |
| Grant date | Jul 28, 2020 |
| Priority date | — |
| Expiry date | Sep 26, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/30
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delta-sigma modulator includes a first integrator and a comparator. The comparator's positive input couples to the first integrator's positive output, and the comparator's negative input couples to the first integrator's negative output. A first current DAC comprises a current source device, and first and second transistors. The first transistor has a first transistor control input and first and second current terminals. The first current terminal couples to the current source device, and the second current terminal couples to the first integrator positive output. The second transistor has a second transistor control input and third and fourth current terminals. The third current terminal couples to the current source device, and the fourth current terminal couples to the first integrator negative output. A first capacitive device couples to the second transistor control input and to both the second current terminal and the first integrator positive output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.