Higher-order network embedding
US10728105B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2018 |
| Grant date | Jul 28, 2020 |
| Priority date | — |
| Expiry date | Dec 22, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/042
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In implementations of higher-order network embedding, a computing device maintains interconnected data in the form of a graph that represents a network, the graph including nodes that each represent entities in the network and node associations that each represent edges between the nodes in the graph. The computing device includes a network embedding module that is implemented to determine a frequency of k-vertex motifs for each of the edges in the graph, and derive motif-based matrices from the frequency of each of the k-vertex motifs in the graph. The network embedding module is also implemented to determine a higher-order network embedding for each of the nodes in the graph from each of the motif-based matrices. The network embedding module can then concatenate the higher-order network embeddings into a matrix representation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.