Migrating operating system interference events to a second set of logical processors along with a set of timers that are synchronized using a global clock
US10733032B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2017 |
| Grant date | Aug 4, 2020 |
| Priority date | — |
| Expiry date | Dec 2, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4818
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, information processing system, and computer program product are provided for managing operating system interference on applications in a parallel processing system. A mapping of hardware multi-threading threads to at least one processing core is determined, and first and second sets of logical processors of the at least one processing core are determined. The first set includes at least one of the logical processors of the at least one processing core, and the second set includes at least one of a remainder of the logical processors of the at least one processing core. A processor schedules application tasks only on the logical processors of the first set of logical processors of the at least one processing core. Operating system interference events are scheduled only on the logical processors of the second set of logical processors of the at least one processing core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.