Effective chip yield for artificial intelligence integrated circuit with embedded memory
US10733039B2 · kind B2 · utility
0Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2018 |
| Grant date | Aug 4, 2020 |
| Priority date | — |
| Expiry date | Jan 28, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This disclosure relates to testing of integrated artificial intelligence (AI) circuit with embedded memory to improve effective chip yield and to mapping addressable memory segments of the embedded memory to multilayer AI networks at the network level, layer level, parameter level, and bit level based on bit error rate (BER) of the addressable memory segments. The disclosed methods and systems allows for deployment of one or more multilayer AI networks in an AI circuit with sufficient model accuracy even when the embedded memory has an overall BER higher than a preferred overall threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.