Microcomputer
US10733125B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2019 |
| Grant date | Aug 4, 2020 |
| Priority date | — |
| Expiry date | Aug 23, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microcomputer including first and second CPUs is provided. The first and second CPUs may execute identical control programs in parallel. The microcomputer may control a write access by the first or second CPU. The microcomputer may compare an output of the first CPU with an output of the second CPU. Data is written to a write target unit. The microcomputer outputs a write response signal to the first and second CPUs when a data write destination of the first and second CPUs is the write target unit. The microcomputer outputs an abnormality determination signal when data output from the first CPU mismatches with data output from the second CPU. The microcomputer writes the data to the write target unit when the data write destination of the first and second CPUs is the write target unit and the abnormality determination signal is not input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.