Low speed bus interface
US10733132B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2018 |
| Grant date | Aug 4, 2020 |
| Priority date | — |
| Expiry date | Aug 3, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0058
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, apparatus, and systems for transferring data between a first and second module are provided. In one aspect, a method includes receiving, by a virtual controller register, outbound data; arbitrating, at a virtual arbitrate, the outbound data; transmitting, from the virtual controller register to the master low speed bus (LSB) frame/de-frame, the outbound data; adding, at the master LSB frame/de-frame, identification data to the outbound data to create an outbound data frame; transmitting, from the master LSB frame/de-frame to a slave LSB frame/de-frame, the outbound data frame; parsing, at the slave LSB frame/de-frame, the outbound data frame into parsed outbound data; arbitrating the parsed outbound data; transmitting, from the slave LSB frame/de-frame to the target controller register, the parsed outbound data; and receiving, at a target controller port from the target controller register, the parsed outbound data for transmitting to the slave device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.