Patent · US Active

Counter integrity tree for memory security

US10733313B2 · kind B2 · utility

0Cited by

2References

20Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Prakash S. Ramrakhyani · Austin, US
Roberto Avanzi · Munich, DE
Wendy Arnott Elsasser · Austin, US

Key dates

Filing date	Feb 9, 2018
Grant date	Aug 4, 2020
Priority date	—
Expiry date	Jan 14, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG06F21/78
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A counter integrity tree for memory security includes at least one split-counter node specifying at least two counters each defined as a combination of a major count value shared between the at least two counters and a respective minor count value specified separately for each of the at least two counters. This increases the number of child nodes which can be provided per parent node of the tree, and hence reduces the number of tree levels that have to be traversed in a tree covering a given size of memory region. The minor counter size can be varied dynamically by allocating nodes in a mirror counter integrity tree for accommodating larger minor counters which do not fit in the corresponding node of the main counter integrity tree.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.