Multi-level cell programming using optimized multiphase mapping with balanced Gray code
US10734071B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2018 |
| Grant date | Aug 4, 2020 |
| Priority date | — |
| Expiry date | Dec 13, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5644
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are systems and methods for providing programming of multi-level memory cells using an optimized multiphase mapping with a balanced Gray code. A method includes programming, in a first phase, a first portion of data into memory cells in a first-level cell mode. The method may also include reading, from the memory cells, the programmed first portion of the data. The method may also include programming, in a second phase, a second portion of the data into the memory cells in a second-level cell mode, wherein programming the second phase is based on applying, to the read first portion of the data, a mapping from the first-level cell mode to the second-level cell mode. The mapping may be selected based on minimizing an average voltage change of the memory cells from the first to second phase while maintaining a balanced Gray code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.