Parallelisable method for integrating power chips and power electronics
US10734368B2 · kind B2 · utility
1Cited by
2References
13Claims
0Family size
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Key dates
| Filing date | Dec 5, 2017 |
| Grant date | Aug 4, 2020 |
| Priority date | — |
| Expiry date | Dec 5, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10166
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The method comprises the steps of 1) producing first and second blanks (EB1) including reserved-space defining means (HM1, HM2), by laminating insulating and conductive inner layers (PP, CP) on copper plates forming a base (MB1), at least one electronic chip being sandwiched between the blanks, said blanks being produced such that their upper lamination surfaces have matching profiles, 2) stacking and fitting the blanks via their matching profiles, and 3) press-fitting the blanks to form a laminated sub-assembly for an integrated power electronics device. The method uses IMS-type techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.