Semiconductor memory device and conductive structure
US10734493B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2018 |
| Grant date | Aug 4, 2020 |
| Priority date | — |
| Expiry date | Jul 9, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
Abstract
A semiconductor memory device may include a substrate, gate electrode structures stacked on the substrate, insulation patterns between the gate electrode structures, vertical channels penetrating through the gate electrode structures and the insulation patterns, and a data storage pattern. The vertical channels may be electrically connected to the substrate. The data storage pattern may be arranged between the gate electrode structures and the vertical channels. Each of the gate electrode structures may include a barrier film, a metal gate, and a crystal grain boundary plugging layer. The crystal grain boundary plugging layer may be between the barrier film and the metal gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.