Interference reduction with optimized bandwidth utilization
US10735087B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2017 |
| Grant date | Aug 4, 2020 |
| Priority date | — |
| Expiry date | Aug 2, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W72/046
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A computer comprises a processor programmed to identify a plurality of sets of channels. Each set of channels includes first, second and third channels. The first and second channels in each set include uplinks respectively in first and second neighbor beams and have a first bandwidth overlap. The first and third channels in each set share a target and a third downlink included in the third channel has a second bandwidth overlap with a first downlink included in the first channel. the second bandwidth overlap includes a bandwidth corresponding to at least a portion the first bandwidth overlap, such that a signal spectrum in the first bandwidth overlap is included in the second bandwidth overlap. The computer is further programmed to optimize a bandwidth reduction across the plurality of sets of channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.