Computing device using bypass assembly
US10739828B2 · kind B2 · utility
6Cited by
248References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 4, 2016 |
| Grant date | Aug 11, 2020 |
| Priority date | — |
| Expiry date | May 4, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01R13/512
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A computing device includes a first connector near a first wall. The first connector is in communication with a chip package positioned apart for the first wall via a first cable. The chip package includes a chip supported by a support layer. The chip can be supported by a substrate and/or a circuit board. A second connector can be positioned near a second wall and can also be in communication with the chip package via a second cable. If desired, the substrate or circuit board can include a signal board connector that is configured to engage board connectors terminated to ends of the first and second cables.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.