System, apparatus and method for optimized throttling of a processor
US10739844B2 · kind B2 · utility
2Cited by
23References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 2, 2018 |
| Grant date | Aug 11, 2020 |
| Priority date | — |
| Expiry date | Aug 3, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a processor includes: a plurality of processing elements to perform operations; a power management agent (PMA) coupled to the plurality of processing elements to control power consumption of the plurality of processing elements; and a throttling circuit coupled to the PMA. The throttling circuit is to determine a throttling power level for the plurality of processing elements based at least in part on translation information communicated from the PMA. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.