Flush-recovery bandwidth in a processor
US10740140B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2018 |
| Grant date | Aug 11, 2020 |
| Priority date | — |
| Expiry date | Jan 26, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system, processor, and method for processing information is disclosed that includes at least one computer processor for processing instructions, the processor having a history buffer having a plurality of entries for storing information associated with a processor instruction evicted from a logical register, the history buffer having at least one recovery port; a logical register mapper for recovering information from the history buffer, the mapper having restore ports to recover information from the history buffer; and a restore multiplexor configured to receive as inputs information from one or more of the history buffer recovery ports, and configured to output information to one or more of the logical register mapper restore ports. The processor, system and/or method configured to improve flush recovery bandwidth.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.