Cache-based trace replay breakpoints using reserved tag field bits
US10740220B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 27, 2018 |
| Grant date | Aug 11, 2020 |
| Priority date | — |
| Expiry date | Oct 17, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Performing breakpoint detection via a cache includes detecting an occurrence of a memory access and identifying whether any cache line of the cache matches an address associated with the memory access. When a cache line does match the address associated with the memory access no breakpoint was encountered. When no cache line matches the address associated with the memory access embodiments identify whether any cache line matches the address associated with the memory access when one or more flag bits are ignored. When a cache line does match the address associated with the memory access when the one or more flag bits are ignored, embodiment perform a check for whether a breakpoint was encountered. Otherwise, embodiments process a cache miss.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.