Virtual processor cache reuse
US10740234B2 · kind B2 · utility
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3References
20Claims
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Key dates
| Filing date | Sep 4, 2018 |
| Grant date | Aug 11, 2020 |
| Priority date | — |
| Expiry date | Feb 7, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An approach is provided in which a first core broadcasts a cache line request in response to detecting a cache miss corresponding to a first virtual central processing unit (VCPU) executing on the first core. Next, the first core receives a cache line response from the second core responding to the cache line request that includes tag extension data. The first core determines a cache miss type of the cache miss based on the tag extension data and, in turn, sends the cache miss type to a hypervisor that utilizes the cache miss type during a future VCPU dispatch selection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.