Cache self-clean engine
US10740260B2 · kind B2 · utility
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1References
17Claims
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Key dates
| Filing date | May 12, 2017 |
| Grant date | Aug 11, 2020 |
| Priority date | — |
| Expiry date | May 12, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates Control circuitry that includes a circuit configured to receive a system level cache (SLC) dirty-set request comprising a dirty set flag, a memory address, and an address of a cache line (LA) in a SLC data array. The circuitry converts the memory address to a dynamic random-access memory (DRAM) page address (PA) which identifies a DRAM bank and a DRAM page and identifies either a hit, or no hit, is present according to whether the DRAM PA matches with PA address in any valid entry in a dirty line links cache (DLL$).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.