Differential serial memory interconnect
US10740264B1 · kind B1 · utility
4Cited by
4References
18Claims
0Family size
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Key dates
| Filing date | Apr 29, 2019 |
| Grant date | Aug 11, 2020 |
| Priority date | — |
| Expiry date | Apr 29, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4295
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronous differential memory interconnect may include a bidirectional differential data signal bus, a unidirectional differential command and address bus, and a differential clock signal. Memory read and write data may be transmitted over the data signal bus in a serial fashion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.