Reduced dot product computation circuit
US10740434B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2018 |
| Grant date | Aug 11, 2020 |
| Priority date | — |
| Expiry date | Sep 26, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06V40/172
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments provide an IC for implementing a machine-trained network with multiple layers. The IC includes a set of circuits to compute a dot product of (i) a first number of input values computed by other circuits of the IC and (ii) a set of predefined weight values, several of which are zero, with a weight value for each of the input values. The set of circuits includes (i) a dot product computation circuit to compute the dot product based on a second number of inputs and (ii) for each input value, at least two sets of wires for providing the input value to at least two of the dot product computation circuit inputs. The second number is less than the first number. Each input value with a corresponding weight value that is not equal to zero is provided to a different one of the dot product computation circuit inputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.