Central and delegate security processors for a computing device
US10740494B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2017 |
| Grant date | Aug 11, 2020 |
| Priority date | — |
| Expiry date | Feb 12, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W12/65
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present disclosure describes use of two security processors for a mobile device. In some aspects, a first security processor device embodied in a security component of an apparatus receives a user input via an input device and transmits a security condition signal to a second security processor device embodied in a System on Chip (SoC) component of the apparatus, causing the SoC component to perform a security operation. In other aspects, the first security processor receives a signal via a sensor device sensing environmental conditions surrounding the apparatus and, in response, transmits a security condition signal to the second security processor, causing the SoC component to perform a security operation. The security operation is directly controlled, maintained, and implemented by the second security processor embodied in the SoC component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.