Method of generating a 3D circuit layout from a 2D circuit layout
US10740528B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2018 |
| Grant date | Aug 11, 2020 |
| Priority date | — |
| Expiry date | Jul 5, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of generating, by a computing device, a 3D circuit layout based on a 2D circuit layout, the method comprising: assigning cells of first and second groups of circuit cells of the 2D circuit layout to first and second levels of the 3D circuit layout, the assignment of each circuit cell of the first and second groups being performed by: selecting, among at least one first row of a first level of the 3D circuit layout and at least one second row of a second level of the 3D circuit layout, the row having the greatest available space; and assigning the circuit cell to the selected row; and transmitting the 3D circuit layout to a manufacturing plant for fabrication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.