Three-dimensional semiconductor memory devices
US10741577B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2018 |
| Grant date | Aug 11, 2020 |
| Priority date | — |
| Expiry date | Nov 5, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/015
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional semiconductor memory device may include a substrate comprising a cell array region and a connection region, an electrode structure including a plurality of gate electrodes sequentially stacked on a surface of the substrate and extending from the cell array region to the connection region, a first source conductive pattern between the electrode structure and the substrate on the cell array region, and a cell vertical semiconductor pattern and a first dummy vertical semiconductor pattern that penetrate the electrode structure and the first source conductive pattern and extend into the substrate. The cell vertical semiconductor pattern may contact the first source conductive pattern. The first dummy vertical semiconductor pattern may be electrically insulated from the first source conductive pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.