Signal conditioning in a serial data link
US10742391B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2019 |
| Grant date | Aug 11, 2020 |
| Priority date | — |
| Expiry date | Mar 20, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A signal conditioner for use in a serial data communications link. The signal conditioner including a tunable delay element responsive to a tuning signal to provide time domain delay modulation of the input data signals to generate conditioned (output) data signals, and phase comparator circuitry to generate the delay tuning signal based on a detected phase error between feedback conditioned data signals, and a reference signal. The tunable delay element and the phase comparator circuitry forming a delay-locked tuning loop to phase lock the conditioned data signals to the reference signal, independent of voltage domain frequency response. An example signal conditioner is a jitter attenuator/cleaner, where the bandwidth of the reference signal is lower than the bandwidth of the delay-locked tuning loop, to provide a low-jitter reference signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.