Semiconductor device having overlay pattern
US10747123B2 · kind B2 · utility
2Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2018 |
| Grant date | Aug 18, 2020 |
| Priority date | — |
| Expiry date | Nov 20, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54426
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A semiconductor device includes a semiconductor substrate including an in-cell area and a scribe lane defining the in-cell area, a first overlay pattern on the semiconductor substrate, and a second overlay pattern adjacent to the first overlay pattern, wherein the first overlay pattern is a diffraction-based overlay (DBO) pattern and the second overlay pattern is a scanning electron microscope (SEM) overlay pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.