Patent · US Active

Multichip reference logging synchronization

US10747259B2 · kind B2 · utility

0Cited by

1References

20Claims

0Family size

Assignee

Intel IP Corporation · US

Inventors

Uwe Schumacher · Soest, DE
Peter Lachner · Heroldstatt, DE
Andrej Tkalcec · Karlsruhe, DE
Donald Korinke · Vancouver, US

Key dates

Filing date	Dec 29, 2017
Grant date	Aug 18, 2020
Priority date	—
Expiry date	Jun 5, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG06F2201/86
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Herein is disclosed a multichip reference logging system comprising a control circuit, configured to generate a reference signal; a first chip, configured to generate a first operations log, the first chip further comprising a first reference circuit, configured to receive the reference signal and to create a first reference event in response to the received reference signal; a memory associated with the first chip, configured to store the first reference event within the first operations log; a second chip, configured to generate a second operations log, the second chip further comprising a second reference circuit, configured to receive the reference signal and to create a second reference event in response to the received reference signal; and a memory associated with the second chip, configured to store the second reference event within the second operations log.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.