Computer architecture for high-speed, graph-traversal
US10747433B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Feb 21, 2018 |
| Grant date | Aug 18, 2020 |
| Priority date | — |
| Expiry date | Nov 26, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/6023
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A computer architecture for graph-traversal provides a processor for bottom-up sequencing through the graph data according to vertex degree. This ordered sequencing reduces redundant edge checks. In one embodiment, vertex adjacency data describing the graph may be allocated among different memory structures in the memory hierarchy to provide faster access to vertex data associated with vertices of higher degree reducing data access time. The adjacency data also may be coded to provide higher compression in memory of vertex data having high vertex degree.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.