Multilevel fault simulations for integrated circuits (IC)
US10747633B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2018 |
| Grant date | Aug 18, 2020 |
| Priority date | — |
| Expiry date | Sep 24, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments include apparatuses, methods, and systems for testing an IC of an in-vehicle system of a CA/AD vehicle includes a storage device and processing circuitry coupled with the storage device. A gate level fault group is provided to include one or more gate level faults of a fault model associated to a gate level circuit element of the gate level netlist of the IC with substantially same fault controllability or observability characteristics. A correlated RTL fault group is determined to be associated to a RTL circuit node, where the RTL circuit node of the RTL netlist corresponds to the gate level circuit element. Other embodiments may also be described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.