System and method for intelligent tile-based prefetching of image frames in a system on a chip
US10747671B1 · kind B1 · utility
1Cited by
0References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2019 |
| Grant date | Aug 18, 2020 |
| Priority date | — |
| Expiry date | Feb 6, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An intelligent tile-based prefetching solution executed by a compression address aperture services linearly addressed data requests from a processor to memory stored in a memory component having a tile-based address structure. The aperture monitors tile reads and seeks to match the tile read pattern to a predefined pattern. If a match is determined, the aperture executes a prefetching algorithm uniquely and optimally associated with the predefined tile read pattern. In this way, tile overfetch is mitigated while the latency on first line data reads is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.