Identification of hotspots in congestion analysis during physical design of integrated circuit
US10747935B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2019 |
| Grant date | Aug 18, 2020 |
| Priority date | — |
| Expiry date | Jan 4, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of performing physical design of an integrated circuit includes subdividing each metal layer of a plurality of metal layers of the integrated circuit into a plurality of g-cells. Each metal layer has either horizontal or vertical tracks, the g-cells of the metal layers with horizontal tracks have vertical edges between adjacent ones of the g-cells, and the g-cells of the metal layers with vertical tracks have horizontal edges between adjacent ones of the g-cells. The method includes determining congestion for each metal layer as congestion values associated with the horizontal edges or the vertical edges of the metal layer, identifying hotspots for each metal layer based on the congestion values of the metal layer, determining a penalty associated with the hotspots of each metal layer, determining a congestion metric for each metal layer based on the penalty, and performing routing of the wires based on the congestion metric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.